This application claims priority of Singapore Application No. 9804835-8 filed Dec. 28, 1998.
Not applicable.
1. Field of the Invention
The present invention generally relates to transitioning a computer system between modes of operation. More particularly, the invention relates to transitioning a portable computer between high performance and low power modes of operation. Still more particularly, the invention relates to generating a break event to alert the computer system""s power management logic that the transition between modes of operation has completed.
2. Background of the Invention
Computer systems require electrical power to operate. Portable computers (xe2x80x9claptopsxe2x80x9d) can operate either from alternating current (xe2x80x9cACxe2x80x9d) power from a wall plug or direct current (xe2x80x9cDCxe2x80x9d) power from a battery. Because batteries only hold enough energy for the computer to operate for a finite period of time, it is desirable to make the batteries last as long as possible. Increasing the time in which a battery can provide usable power can be accomplished either by providing a higher density battery (i.e., a battery that provides more energy per unit volume) or designing the computer system to require less power to operate.
Desktop personal computers generally operate only from AC power. Even though such computers generally do not operate off of battery power, it nevertheless is desirable to provide a desktop system that consumes as little electrical power as possible. Reducing the electrical power demands of computers, and other electrical equipment, helps to alleviate the environmental concerns caused by electrical power plants.
One technique for reducing the power demand of a computer is to lower the frequency of the central processing unit (xe2x80x9cCPUxe2x80x9d) clock signal. The CPU clock signal is a periodic signal which oscillates between two voltages at a specified rate and controls the internal timing of the CPU. That rate is referred to as the xe2x80x9cfrequencyxe2x80x9d or xe2x80x9cspeedxe2x80x9d of the clock signal. A 400 MHz CPU clock, for example, oscillates between two voltage levels at a rate of 400 million times per second. CPUs generally consume less power when operated using clock signals at lower speeds. A CPU operating from a 300 MHz clock signal generally consumes less power then the same CPU operating at 400 MHz. Additionally and/or alternatively, computer system power consumption can be reduced by having the electrical devices that comprise the computer operate a lower voltage. All else being equal, a 5V processor consumes more power than a 3.3V processor.
Accordingly, one way to conserve power in a computer system is for the computer to transition from a higher power mode of operation to a lower power mode of operation in certain, pre-defined situations. The situations may include disconnecting the AC power cord from a portable computer, thereby requiring the computer to operate from a battery. Performance is increased while the computer operates off AC power by running the CPU at its maximum rated speed. While operating off battery power, the battery charge is conserved by running the CPU at a slower speed and/or operating the CPU at a lower voltage. If the portable computer includes a fan to help cool the electronics, the fan may be turned off to further conserve battery power. Without the fan helping to cool the computer, the electronics may become warmer than desirable. Reducing the CPU voltage ameliorates this problem. Of course, once the AC power is restored, the computer should transition back to the higher power mode of operation.
The Intel Corp. as suggested an initiative called xe2x80x9cGeyserville Technologyxe2x80x9d which permits a computer to transition between various power modes of operation. Intel chip sets (e.g. processors and bridge devices) that implement Geyserville technology include logic that initiates transitions between power modes of operation. In a xe2x80x9chigh performancexe2x80x9d mode, the CPU operates at full speed and a higher voltage than when operating in a xe2x80x9clow powerxe2x80x9d mode in which the speed of the CPU clock signal and operational voltage are reduced. Transitioning a computer between operational modes in accordance with the Geyserville Technology is often referred to as a xe2x80x9cGeyserville mode switch.xe2x80x9d Descriptions of Intel chip sets that implement the Geyserville technology include xe2x80x9cIntel Pentium(copyright) II Processor Mobile Module: Mobile Module Connector 2 (MMC-2)xe2x80x9d dated August 1998 and the xe2x80x9c82371AB PCI-to-ISA/IDE XCELERATOR (PIIX4)xe2x80x9d dated April 1997, both of which are incorporated herein by reference.
It has been observed that in certain situations a computer that implements the standard Geyserville mode switching logic may cause various problems preventing the computer from operating normally. These problems occur in situations in which the computer is in the process of transitioning from one mode of operation to another mode when the CPU is requested to perform another function. For example, a Geyserville interrupting event may undesirably experience latency and retries may be required prolonging the Geyserville mode switch.
One solution to this problem is for the user to not use the computer in such a way as may disturb the CPU during the Geyserville mode switch. This approach places an undesirable burden on the human user to remember not to press a key or other input device during a Geyserville mode switch. Further, in some situations, such as when the computer""s modem receives an incoming communication over a telephone line during a Geyserville mode switch, the computer""s hardware resources, not the human user, causes the disturbance to the CPU during the mode switch. It would be better, however, to provide a computer system in which the CPU cannot be disturbed during the mode switch without the problems of conventional systems. Despite the advantages such a computer system would offer, to date no such system is known to exist.
The deficiencies of the prior art described above are solved in large part by a computer system that can operate in one of a plurality of modes, such as a high performance mode and a low power mode. In the high performance mode, the CPU clock is faster than in the low power mode. The CPU voltage may also be higher in the high performance mode than in the low power mode. The low power mode may be desirable for a portable computer operating from battery power in order to conserve the battery""s charge. The computer system preferably transitions the CPU to a xe2x80x9csleepxe2x80x9d state during the mode switch and, in accordance with the preferred embodiment, precludes devices not associated with the mode transition from xe2x80x9cwakingxe2x80x9d the CPU before the mode switch has completed. Accordingly, only logic that detects the end of the mode switch can break the computer out of the sleep state. Further, completion of the mode switch is not slowed down by non-mode switch related events.
The computer system preferably includes a CPU mobile module coupled to a bus bridge device, stop clock logic and a clock generator. The bus bridge device includes registers that can be programmed by the CPU mobile module to enable a break event that preferably can only be initiated by the CPU mobile module upon completion of a mode switch. Once the mode switch is complete, the CPU mobile module asserts a general purpose input signal to the bus bridge device to initiate a break event. The particular general purpose input signal used to initiate the break event preferably is not shared by devices other than the CPU mobile module and thus, only the CPU mobile module can initiate the break event.
By enabling and generating a break event that is not shared by devices other than the CPU mobile module, the problems described above regarding conventional computer systems are mitigated or avoided altogether. The various characteristics described above, as well as other features, will be readily apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments of the invention, and by referring to the accompanying drawings.